This paper presents a hardware processor for 100 Gbps wireless data link layer. A serial Reed-Solomon decoder requires a clock\nof 12.5GHz to fulfill timings constraints of the transmission. Receiving a single Ethernet frame on a 100Gbps physical layer may\nbe faster than accessing DDR3 memory. Processing so fast streams on a state-of-the-art FPGA (field programmable gate arrays)\nrequires a dedicated approach. Thus, the paper presents lightweight RS FEC engine, frames fragmentation, aggregation, and a\nprotocol with selective fragment retransmission. The implemented FPGA demonstrator achieves nearly 120 Gbps and accepts bit\nerror rate (BER) up to 2
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